Please refer to FIG. 1 which illustrates the circuit of a pixel unit in a conventional thin film transistor liquid crystal display (TFT-LCD). The pixel unit includes a TFT unit 11, a pixel 12 and a storage capacitor 15. The TFT unit 11 is used as a switch unit controlled by a voltage Vs of scan line to turn on or off. The pixel 12 includes a pixel electrode 131, a common electrode 132 and liquid crystal layer 133. When the TFT unit 11 is switched ON, a voltage Vd of data line is applied between the pixel electrode 131 and the common electrode 132 of the pixel 12 for changing the orientation status of the liquid crystal molecules of liquid crystal layer 133. In such way, the transmittance of the pixel 12 can be adjusted so as to change the illumination of that pixel in response to the light emitted from a backlight source 14. The storage capacitor 15 electrically connected to the TFT unit 11 and the pixel 12 is used to store voltage Vd between the pixel electrode 131 and the common electrode 132 of the pixel 12.
According to a conventional process for producing a low temperature polysilicon thin film transistor (LTPS-TFT), the TFT unit 11 is implemented as an N-channel metal oxide semiconductor field effect transistor (NMOS-FET). However, when the channel of NMOS-FET is largely shortened due to high integrity, a so-called “hot electron effect” is likely to occur so as to affect the normal operation of the device. For solving this problem, NMOS-FET having a lightly doped drain (LDD) structure has been developed to be used in the LTPS-TFT liquid crystal display (LCD). During the procedure for forming the LDD structure, a photo misalignment problem occurs. Hence, a conventional self-align intra-gate TFT is developed.
FIGS. 2A and 2B show a conventional procedure for producing the self-align intra-gate TFT. As shown in FIG. 2A, the TFT includes an LTPS layer 21 formed on a substrate 20, an insulating layer 24 formed on the LTPS layer 21 and two sub-gate electrodes 211 and 212 formed on the insulating layer 24. After the first ion implantation procedure, two source/drain regions 201 and 202 and a self-align intra-gate lightly doping (SA-IGLD) region 22 are doped. Subsequently, a mask 23 is applied over and between two sub-gate electrodes 211 and 212 and then the second ion implantation procedure is performed. Hence, two source/drain electrodes are formed by heavily doping the source/drain regions 201 and 202, while the SA-IGLD region 22 covered by the mask 23 remains lightly doped. The resulting TFT structure has electric features comparable with that having a lightly doping drain (LDD) structure. However, it is still necessary to perform two ion implantation procedures with different implantation energies and dosages to accomplished the above structure. Consequently, such complicated procedures are involved and the production rate is reduced.
Therefore, the purpose of the present invention is to develop a TFT structure and a method for manufacturing the TFT to deal with the above situations encountered in the prior art.